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Digital Logic Design Lab (訾頛航身閮撖衣), Spring 2010


Announcement
Lecturing Information
Slides
Grading
Slides (隤脩敶梁)
Lecturing Slides (銝隤脫敶梁)
  1. 撖衣 [2010/02/26]
  2. 箇撖阡閮剖隤霅 - 隞嗉其蝝 (Lab 1) [2010/03/04]
  3. 訾IC隤霅頛舐皜祈岫 (Lab 2) [2010/03/05]
  4. Stistate, Fanout, OC Chip, TTL-CMOS Interface (Lab 3) [2010/03/12]
  5. Combonational Logic: SOP, POS, AOI, ALL-NAND, and ALL-NOR (Lab 4) [2010/03/19]
  6. DE0 with QuartusII (Lab 5) [2010/03/26]
  7. VHDL Introduction (Lab 6) [2010/04/02]
  8. Combinational Logic Functions (Lab 7) [2010/04/09]
  9. MUX/DMUX and Full Adder (Lab 8) [2010/04/16]
  10. Sequential Logic: Latch (Lab 9) [2010/04/30]
  11. Sequential Logic: Flip Flop (Lab 10) [2010/05/07]
  12. Shift Registers (Lab 11) [2010/05/14]
  13. State Machine (Lab 12) [2010/05/21]
  14. Memory (Lab 13) [2010/05/28]
  15. Microprocessors (Lab 14) [2010/06/14]


Terasic DE0 FPGA Development Board (FPGA Chip: EP3C16F484C6)


Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson
     


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Yuan-Hao Chang
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