Home
Contact Me
Digital Logic Design Lab (
訾頛航身閮撖衣
), Spring 2010
Announcement
Lecturing Information
Slides
Grading
Slides (
隤脩敶梁
)
Lecturing Slides (銝隤脫敶梁)
撖衣
[2010/02/26]
箇撖阡閮剖隤霅 - 隞嗉其蝝 (Lab 1)
[2010/03/04]
訾IC隤霅頛舐皜祈岫 (Lab 2)
[2010/03/05]
Stistate, Fanout, OC Chip, TTL-CMOS Interface (Lab 3)
[2010/03/12]
Combonational Logic: SOP, POS, AOI, ALL-NAND, and ALL-NOR (Lab 4)
[2010/03/19]
DE0 with QuartusII (Lab 5)
[2010/03/26]
VHDL Introduction (Lab 6)
[2010/04/02]
Combinational Logic Functions (Lab 7)
[2010/04/09]
MUX/DMUX and Full Adder (Lab 8)
[2010/04/16]
Sequential Logic: Latch (Lab 9)
[2010/04/30]
Sequential Logic: Flip Flop (Lab 10)
[2010/05/07]
Shift Registers (Lab 11)
[2010/05/14]
State Machine (Lab 12)
[2010/05/21]
Memory (Lab 13)
[2010/05/28]
Microprocessors (Lab 14)
[2010/06/14]
Terasic DE0 FPGA Development Board (FPGA Chip: EP3C16F484C6)
DE0 Installation (DE0 Getting Started)
DE0 User Manual
DE0 Control Panel
DE0 Schematic
Page Top
Yuan-Hao Chang
Copyright © All Rights Reserved.