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Digital Logic Design Lab (訾頛航身閮撖衣), Spring 2011


Announcement
Lecturing Information
Slides
Grading
Slides (隤脩敶梁)
Lecturing Slides (銝隤脫敶梁)
  1. Introduction to Components and Equipments
  2. Introduction to Digital IC
  3. Logic Gates
  4. Combinational Logic
  5. DE0 with QuartusII
  6. VHDL Introduction
  7. Combinational Logic Functions
  8. MUX/DMUX and Full Adder
  9. Sequential Logic - Latch
  10. Sequential Logic - Flip Flop
  11. Shift Registers
  12. State Machine
  13. Memory
  14. Microprocessors

Terasic DE0 FPGA Development Board (FPGA Chip: EP3C16F484C6)

VHDL References
Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson
     


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Yuan-Hao Chang
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