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| Publications |
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| Journal Articles | | |
| 1. |
H.Chen, J. Yu, C. Hang, P.C. Yew and B. Zang, "Dynamic Software Updating Using a Relaxed Consistency Model," IEEE Trans. on Software Engineering, 2010. |
| 2. |
P. Woodward, J. Jayaraj, P.H. Lin, P.C. Yew, "Moving Scientific Codes to IBM Cell Processor and Other Multicore Microprocessor CPUs," IEEE Computing In Science and Engineering, pages 16-25, November 2008. |
| 3. |
S.V. Kodakara, J. Kim, D.J. Lilja, D. Hawkins, W.C. Hsu, and P.C. Yew, "CIM: A Reliable Metric for Evaluating Program Phase Classifications," IEEE Computer Architecture Newsletter, 2007. |
| 4. |
J.Lin, W.C. Hsu, P.C. Yew, R.D.C. Ju, and T.F. Ngai, "Recovery Code Generation for," ACM Transactions on Architecture and Code, volume 3, number 1, pages 67-89, March 2006. |
| 5. |
J.S.Kong, P.C.Yew and G.H.Lee, "Minimizing the Directory Size for Large-Scale Shared-Memory Multiprocessors," IEICE Trans. on Information and Systems, volume E88-D, number 112533, pages 2533-2543, November 2005. |
| 6. |
J.Lin, T.Chen, W.C. Hsu, P.C. Yew, R.D.C. Ju, T.F. Ngai and S. Chan, "A Compiler Framework for Speculative Optimizations," ACM Transactions on Architecture and Code, volume 1, number 3, pages 247-271, September 2004. |
| 7. |
J. Lu, H. Chen, P.C.Yew, W.C. Hsu, "Design and Implementation of a Lightweight Dynamic Optimization System," Journal of Instruction-Level Parallelism, volume 6, 2004. |
| 8. |
P.Y. Tang and P.C. Yew, "Interprocedural Induction Variable Analysis," International Journal of Foundation of Computer Science, volume 14, number 3, pages 405-423, June 2003, World Scientific |
| 9. |
S.J. Lee and P.C. Yew, "On Augmenting Trace Cache for High-Bandwidth Value Predication," IEEE Tran. on Computers, volume 51, number 9, pages 1074-1088, September 2002. |
| 10. |
H.B. Lim and P.C. Yew, "Efficient Integration of Compiler-Directed Cache Coherence and Data Prefetching," Journal of Parallel and Distributed Computing, volume 61, number 12, pages pp. 1775-1802, December 2001. |
| 11. |
S.J. Lee and P.C. Yew, "On Table Bandwidth and Its Update Delay for Value Prediction on Wide-Issue ILP Processors," IEEE Tran. on Computers, volume 50, number 8, pages 847-852, August 2001. |
| 12. |
S.Y.Cho, P.C. Yew and G. Lee, "A High-Bandwidth Memeory Pipeline for Wide-Issue Processors," IEEE Tran. on Computers, volume 50, number 7, pages 709-723, July 2001. |
| 13. |
L.Choi and P.C. Yew, "Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance," Journal of Parallel and Distributed Computing, volume 11, number 9, pages 879-896, September 2000. |
| 14. |
L.Choi and P.C. Yew, "Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors," IEEE Trans. on Parallel and Distributed Systems, volume 11, number 4, pages 375-394, April 2000. |
| 15. |
I.H. Kazi, et al., "JaViz: A Client/Server Java Profiling Tool," a special issue on Java technology in IBM Systems Journal, volume 39, number 1.1, 2000. |
| 16. |
J.Y.Tsai, et al., "The Superthreaded Architecture," a special issue on multithreaded architectures in the IEEE Trans. on Computers, volume 48, number 9, pages 881-903, September 1999. |
| 17. |
D.K. Chen and P.C. Yew, "Redundant Synchronization Elimination for Doacross Loops," IEEE Trans. on Parallel and Distributed Systems, volume 10, number 5, May 1999. |
| 18. |
H.B.Lim and P.C. Yew, "Maintaining Cache Coherence Through Compiler-Directed Data Prefetching," Journal of Parallel and Distributed Computing, volume 53, number 2, pages 144-173, September 1998. |
| 19. |
J.Y. Tsai, Z. Jiang, and P.C. Yew, "Compiler Techniques for the Superthreaded Architectures," a Special Issue on Languages and Compilers for Parallel Computing , June 1998, International Journal of Parallel Programming |
| 20. |
J.Y.Tsai, P.C. Yew, et al., "Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading," a special issue in Journal of Information Science and Eng, number 14, pages 205-222, March 1998. |
| 21. |
S.Adve, et al., "The Interaction of Architecture and Compilation Technology for High-Performance Processor Design," IEEE Computers, December 1997. |
| 22. |
J.Y.Tsai and P.C. Yew, "Enhancing Multiple-Path Speculative Execution with Predicate Window Shifting," Journal of Systems Architecture, June 1997. |
| 23. |
W.T. Hsu and P.C. Yew, "Performance Evaluation of Wire-Limited Hierarchical Networks," Journal of Parallel and Distributed Computing, volume 41, pages 156-172, June 1997. |
| 24. |
L.Choi, H.B.Lim and P.C. Yew, "Multiprocessor Cache Coherence: The Compiler-Directed Approach," IEEE Parallel & Distributed Technology, pages 23-35, December 1996. |
| 25. |
D.K. Chen and P.C. Yew, "On Effective Execution of Non-Uniform Doacross Loops," IEEE Trans. on Parallel and Distributed Systems, volume 7, number 5, pages 463-476, May 1996. |
| 26. |
D.K. Poulsen and P.C. Yew, "Integrating Fine-Grained Message Passing in Cache Coherent Shared-Memory Multiprocessors," Journal of Parallel and Distributed Computing, volume 33, number 2, pages 172-188, March 1996. |
| 27. |
J.D. Bruner, C.J. Beckmann, P. Konas, D.K. Poulsen and P.C. Yew, "Chief: A Simulation Environment for Studying Parallel Systems," International Journal of Computer Simulation, volume 6, number 1, pages 89-100, 1996. |
| 28. |
D.J. Lilja and P.C. Yew, "Improving Memory Utilization in Cache Coherence Directories," IEEE Trans. on Parallel and Distributed Systems, volume 4, number 10, pages 1130-1146, October 1993. |
| 29. |
W.T. Hsu and P.C. Yew, "An Effective Synchronization Network for Hot Spot Accesses," ACM Trans. on Computing Systems, volume 10, number 3, pages 167-189, August 1992. |
| 30. |
P. Tang, P.C. Yew, "Software Combining Algorithms for Distributing Hot-Spot Addressing," Journal of Parallel and Distributed Computing, volume 10, number 2, pages 130-139, October 1990. |
| 31. |
Z. Fang, P. Tang, P.C. Yew and C.Q. Zhu, "Dynamic Processor Self-Scheduling for General Parallel Nested Loops," IEEE Tran. on Computers, volume 39, number 7, pages 919-929, July 1990. |
| 32. |
Tim Davis and P.C. Yew, "A Stable Non-Deterministic Parallel Algorithm for General Unsymmetric Sparse LU Factorization," SIAM J. on Matrix Analysis and Applications, volume 2, number 3, pages 383-403, July 1990. |
| 33. |
Z. Shen, Z. Li and P.C. Yew, "An Empirical Study on Program Characteristics for Parallelizing Compilers," IEEE Trans. on Parallel and Distributed Systems, volume 1, number 3, pages 356-364, July 1990. |
| 34. |
Z. Li, P.C. Yew and C.Q.Zhu, "An Efficient Data Dependence Analysis for Parallelizing Compiler," IEEE Trans. on Parallel and Distributed Systems, volume 1, number 1, pages 26-34, January 1990. |
| 35. |
N.F. Tzeng and P.C. Yew and C.Q. Zhu, "Realizing Fault-Tolerant Interconnection Networks via Chaining," IEEE Tran. on Computers, volume 37, number 4, pages 458-462, April 1988. |
| 36. |
Z. Li and P.C. Yew, "Program Parallelization with Interprocedural Analysis," J. of Supercomputing, Kluwer Academic Publishers, pages 225-244, 1988. |
| 37. |
C.Q. Zhu and P.C. Yew, "A Scheme to Enforce Data Dependence on Large Multiprocessor Systems," IEEE Trans. on Software Engineering, volume SE-13, number 6, pages 726-739, June 1987. |
| 38. |
P.C. Yew, N.F. Tzeng and D.H. Lawrie, "Distributing Hot Spot Addressing in Large Scale Multiprocessors," IEEE Tran. on Computers, volume C-36, number 4, pages 388-395, April 1987. |
| 39. |
P.C. Yew, D.A. Padua and D.H. Lawrie, "Stochastic Properties of a Multiple-Layer Single-Stage Shuffle-Exchange Network in a Message Switching Environment," J. of Digital Systems, volume 6, number 4, pages 387-410, 1982. |
| 40. |
P.Y. Chen, D.H. Lawrie, P.C. Yew and D.A. Padua, "Interconnection Networks Using Shuffle," IEEE Computers, volume 14, number 12, pages 55-64, December 1981. |
| 41. |
P.C. Yew and D.H. Lawrie, "An Easily Controlled Network for Frequently Used Permutations," IEEE Tran. on Computers, volume C-30, number 4, pages 296-298, April 1981. |
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| Conference Papers | | |
| 1. |
D. Xu, C. Wu and P.C. Yew, "On Mitigating Memory Bandwidth Contention Through Bandwidth-Aware Scheduling," Proc. of Int'l Conf. on Parallel Architectures and Compiler Techniques (PACT), September 2010. |
| 2. |
Z. Wang, C. Wu and P.C. Yew, "On Improving Heap Memory Layout by Dynamic Pool Allocation," Proc. of the 8^th Annual Intl Symp. on Code Generation and Optimization (CGO), April 2010. |
| 3. |
L. Wang, et. al., "An Adaptive Task Creation Strategy for Work-Stealing Scheduling," Proc. of the 8^th Annual Intl Symp. on Code Generation and Optimization (CGO), April 2010. |
| 4. |
J. Lin and P.C. Yew, "A Compiler Framework for General Memory Layout OptimizationTargeting Structures and Arrays," The 12th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT), 2010. |
| 5. |
H. Chen, L. Yuan, X. Wu, B. Zang, B. Huang, P.C. Yew, "Control Flow Obfuscaton with Information Flow Tracking," Proc. of the 42nd Int'l Symp. on Microarchitecture (MICRO-42), November 2009. |
| 6. |
V. Packirisamy, A. Zhai, W.C. Hsu, P.C. Yew, T.F. Ngai, "Exploring Speculative Parallelism in SPEC2008," Proc. of Intn’l Symp. On Performance Analysis of Systems and Software (ISPASS), April 2009. |
| 7. |
Y. Duan, X. Feng, P.C. Yew, "Detecting and Eliminating Potential Violation of Sequential Consistency for Concurrent C/C++ Programs," Proc. of the 7^th Annual IEEE/ACM Int'l Symp. on Code Generation and Optimization (CGO), March 2009. |
| 8. |
G.J.He, A. Zhai and P.C. Yew, "Ex-Mon: An Architectural Framework for Dynamic Program Monitoring on Multicore Processors," The 12th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT), February 2008. |
| 9. |
V. Packirisamy, Y. Luo, W.L. Hung, A. Zhai, P.C. Yew, and T.F. Ngai, "Efficiency of Thread-Level Speculation in SMT and CMP Architectures – Performance, Power and Thermal Perspective," Proc. of Int’l Conf. on Computer Design (ICCD), 2008, (Best Paper Award) |
| 10. |
H. Chen, X. Wu, L. Yuan, B. Zang, P.C. Yew, F.T. Chong, "From Speculation Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware," 35th ACM/IEEE International Symp. on Computer Architecture (ISCA-35), 2008. |
| 11. |
S.V. Kodakara, J. Kim, W.C. Hsu, D.J. Lilja, P.C. Yew, "Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization," Proc. of Int'l Symp. on Workload Characterization (IIWCS), September 2007. |
| 12. |
H. Chen, R. Chen, F. Zhang, B. Zang and P.C. Yew, "Mercury: Combining Performance with Dependability Using Self-Virtualization," Proc. of Int’l Conf. on Parallel Processing (ICPP), September 2007, (Best Paper Award) |
| 13. |
J.Kim, W.C. Hsu and P.C. Yew, "COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications," Proc. of Int’l Conf. on Parallel Processing (ICPP), September 2007. |
| 14. |
S.J. Lee, H.K. Lee, and P.C. Yew, "Runtime Performance Projection Model for Dynamic Power Management," Proc. of Asia-Pacific Computer Systems Architecture Conference(ACSAC), August 2007. |
| 15. |
J. Kim, S.V. Kodakara, W.C. Hsu, D.J. Lilja, R. Geva, P.C. Yew, "Entropy-Based Profile Characterization and Classification for Automatic Profile Management," Proc. of Asia-Pacific Computer Systems Architecture Conference (ACSAC), August 2007. |
| 16. |
H.Chen, J.Yu, C.Rong, B.Y.Zang and P.C.Yew, "POLUS: A Powerful Live Updating Systems," Proc. of Int'l Conf. on Software Engineering (ICSE), May 2007. |
| 17. |
R. Fu, A. Zhai, P.C.Yew and W.C. Hsu, J.Lu, "Reducing Queueing Stalls Caused by Data Prefetching," The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT), May 2007. |
| 18. |
V. Packirisamy, S.Y. Wang, A. Zhai, W.C. Hsu, P.C. Yew, "Supporting Speculative Multithreading on Simultaneous Multithreaded Processors," Proc. of Int'l Conf. on High Performance Computing (HiPC), December 2006, Bangalore, India |
| 19. |
S.Y. Wang, A. Zhai, P.C. Yew, "Exploiting Speculative Thread-Level Parallelism in Data Compression Applications," Proc. of 19th Workshop on Languages and Compiler for Parallel Computing (LCPC), November 2006, New Orlean, LA |
| 20. |
H.B. Chen, R. Chen, F.Z. Zhang, B.Y. Zang, P.C. Yew, "Live Updating Operating Systems Using Virtualization," 2nd Int'l Conf on Virtual Execution Environments (VEE), June 2006. |
| 21. |
J. Kim, S.V. Kodakara, W.C. Hsu, D.J. Lilja, P.C Yew, "Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations," 2005 International Conference on High Performance Embedded Architectures & Compilers, Lecture Notes in Computer Science, 3793, volume 3793, pages 203 - 217, October 2005, HiPEAC |
| 22. |
X. Dai, A. Zhai, W.C. Hsu and P.C. Yew, "A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion," Proc. of the 3rd Annual IEEE/ACM International Symp. on Code Generation and Optimization (CGO), pages 280-290, March 2005. |
| 23. |
A. Das, J. Lu, H. Chen, J. Kim, P.C. Yew, W.C. Hsu, D.Y. Chen, "Performance of Runtime Optimization on BLAST," Proc. of the 3rd Annual IEEE/ACM International Symp. on Code Generation and Optimization (CGO), pages 86-96, March 2005. |
| 24. |
H. Chen, J. Lu, W.C. Hsu, P.C. Yew, "Continuous Adaptive Object-Code Re-optimization Framework," Ninth Asia-Pacific Computer Systems Architecture Conference (ACSAC), pages pp. 241-255, September 2004. |
| 25. |
T.Chen, J.Lin, X.Dai, W.C. Hsu and P.C. Yew, "Data Dependence Profiling for Speculative Optimizations," Proc. of 14 Int'l Conf. on Compiler Construction (CC), pages pp. 57-62, March 2004. |
| 26. |
J. Lu, H. Chen, R. Fu, W.C. Hsu, B. Othmer and P.C. Yew, "The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System," Proc. of 36th Annual Int'l Symp. on Microarchitecture (MICRO-36), December 2003. |
| 27. |
J.Lin, W.C. Hsu, P.C. Yew, R.D. Ju and T.F. Ngai, "A Compiler Framework for Recovery Code Generation in General Speculative Optimizations," Proc. of ACM-SIGPLAN Conf. on Programming Language Design and Implementation (PLDI), pages 289-299, June 2003. |
| 28. |
J. Lin, T. Chen, W.C. Hsu and P.C. Yew, "Speculative Register Promotion Using Advanced Load Adress Table (ALAT)," Proc. of the 1st IEEE/ACM Int'l Symp. on Code Generation and Optimization (CGO), pages 125-134, March 2003. |
| 29. |
H. Chen, W.C. Hsu, J. Lu, B. Othmer, D.Y. Chen, and P.C. Yew, "Dynamic Trace Selection Using Performance Monitoring Hardware Sampling," Proc. of the 1st IEEE/ACM Int'l Symp. on Code Generation and Optimization (CGO), pages 79-90, March 2003. |
| 30. |
T. Chen, J. Lin, W.C. Hsu and P.C. Yew, "An Empirical Study on the Granularity of Pointer Analysis in C Programs," Proc of the 15th Workshop on Languages and Compilers for Parallel Computing (LCPC), August 2002. |
| 31. |
P.Y.Tang and P.C.Yew, "Interprocedural Induction Variable Analysis," Proc. of 6th Int'l Symp. on Parallel Architectures Algorithms and Networks (I-SPAN), pages 245-250, May 2002. |
| 32. |
T.Chen, J.Lin, W.C.Hsu and P.C. Yew, "An Empirical Study on the Characteristics of Heap-Oriented Pointers in C Programs," Proc. of 6th Int'l Symp. on Parallel Architectures Algorithms and Networks (I-SPAN), pages 251-256, May 2002. |
| 33. |
W.C. Hsu, H. Chen, P.C. Yew and D.Y. Chen, "On the Predictability of Program Behavior Using Different Input Data Sets," Proc. of the 6th Workshop on Interaction Between Compilers and Computer Architectures (INTERACT-6), February 2002. |
| 34. |
S.J. Lee and P.C. Yew, "On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors," Proc. of Int'l Conf. on Parallel architectures and Compiler Techniques(PACT), pages 145-156, October 2000. |
| 35. |
H.B. Lim and P.C. Yew, "Efficient Integration of Compiler-Directed Cache Coherence and Data Prefetching," Proc. of the 2000 Int'l Parallel and Distributed Processing Symposium (IPDPS), pages 331-342, May 2000, (Best Paper Award) |
| 36. |
S.J. Lee, Y. Wang and P.C. Yew, "Decoupled Value Prediction on Trace Processors," Proc. of Int'l Conf on High-Performance Computer Architecture (HPCA-6), pages 231-240, January 2000. |
| 37. |
S.Y. Cho, P.C. Yew and G.H. Lee, "Access Region Locality for High-Bandwidth Processor Memory System Design," Proc. of the 32nd Int'l Symp. on Microarchitecture (MICRO-32), pages 136-146, November 1999. |
| 38. |
B.Zheng, et. al., "Designing the Agassiz Compiler for Concurrent Multithreaded Architectures," Proc. of the 12th Workshop on Languages and Compilers for Parallel Computing (LCPC-12), August 1999. |
| 39. |
S.Y.Cho and P.C. Yew, "Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor," Proc. of the 26th ACM/IEEE International Symp. on Computer Architecture (ISCA-26), pages 100-110, May 1999. |
| 40. |
H.B. Lim and P.C. Yew, "An Integrated Framework for Compiler-Directed Cache Coherence and Data Prefetching," Proc. of the 11th Workshop on Languages and Compilers for Parallel Computing (LCPC-11), August 1998. |
| 41. |
S.Cho, J.Y.Tsai, et.al, "High-Level Information - An Approach for Integrating Front-end and Back-end Compilers," Proc of the 1998 Int'l Conf on Parallel Processing (ICPP), pages pp. 346-355, August 1998. |
| 42. |
J.Y.Tsai, Z.Jiang, E.Ness, and P.C. Yew, "Performance of a Concurrent Multithreaded Processors," Proc. of the 4th International Symposium of High Performance Computer Architecture (HPCA-4), pages 24-34, February 1998. |
| 43. |
J.Y.Tsai, B.Zheng, and P.C.Yew, "Program Optimization for Concurrent Multithreaded Architectures," Proc. of the 10th Workshop on Languages and Compilers for Parallel Computing (LCPC-10), August 1997. |
| 44. |
H.B. Lim, and P.C. Yew, "A Compiler-Directed Cache Coherence Scheme Using Data Prefetching," Proc. of the Int'l Symp. on Parallel Processing (IPPS), pages 643-649, April 1997. |
| 45. |
J.Y. Tsai and P.C. Yew, "The Superthreaded Architecture: Thread Pipelining for Run-Time Data Dependence Checking and Control Speculation," Proc. of the 1996 Int'l Conf. on Parallel architectures and Compiler Techniques (PACT), pages 35-46, October 1996. |
| 46. |
L.Choi and P.C. Yew, "Program Analysis for Cache Coherence: Beyond Procedural Boundaries," Proc. of the 1996 Int'l Conf. on Parallel Processing (ICPP), volume 3, pages 103-114, August 1996. |
| 47. |
H.B. Lim, L. Choi and P.C. Yew, "On Using Data Prefetching for Cache Coherence in Multiprocessors," Proc. of the 9th Workshop on Languages and Compilers for Parallel Computing (LCPC-9), August 1996. |
| 48. |
Z. Li, J.Y. Tsai, X. Wang, P.C. Yew and B. Zheng, "Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support," Proc. of the 9th Workshop on Languages and Compilers for Parallel Computing (LCPC-9), August 1996. |
| 49. |
W.T. Hsu and P.C. Yew, "Let Us Build System-Friendly Networks – Build Them Hierarchically," 1996 ICPP Workshop on Challenges for Parallel Processing, August 1996, invited paper |
| 50. |
L.Choi and P.C. Yew, "Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Evaluation," Proc. of the 23rd ACM/IEEE International Symp on Computer Architecture (ISCA-23), pages 283-294, May 1996. |
| 51. |
L.Choi and P.C. Yew, "Eliminating Stale Data References through Array Data-Flow Analysis," Proc. of the 1996 Int'l Symp. on Parallel Processing (IPPS), pages 4-13, April 1996. |
| 52. |
P. Konas and P.C. Yew, "Processor Self-Scheduling in Parallel Discrete Event Simulation," Proc. of the 1995 Winter Simulation Conference, December 1995. |
| 53. |
L.Choi and P.C. Yew, "Interprocedural Array Data-Flow Analysis for Cache Coherence," Eighth Workshop on Languages and Compilers for Parallel Computing (LCPC-8), August 1995. |
| 54. |
P.Konas and P.C. Yew, "Partitioning for Synchronous Parallel Simulation," Proc. of the ACM/IEEE/SCS 9th Workshop on Parallel and Distributed Simulation, 1995. |
| 55. |
D.Poulsen and P.C. Yew, "Data Prefetching and Data Forwarding in Shared-Memory Multiprocessors," Proc. of the Int'l Conf. on Parallel Processing (ICPP), volume 2, pages 276-280, August 1994. |
| 56. |
D.K.Chen and P.C. Yew, "Statement Reordering for Doacross Loops," Proc. of the Int'l Conf. on Parallel Processing (ICPP), volume 2, pages 24-28, August 1994. |
| 57. |
P. Konas and P.C. Yew, "Improved Parallel Architectural Simulations on Shared-Memory Multiprocessors," Proc. of the ACM/IEEE/SCS 8th Workshop on Parallel and Distributed Simulation, July 1994. |
| 58. |
D.K.Chen and P.C. Yew, "Redundant Synchronization Elimination for Doacross Loops," Prof. of 1994 Int'l Parallel Processing Symp. (IPPS), pages 477-481, April 1994. |
| 59. |
L.Choi and P.C. Yew, "A Compiler-Directed Cache Coherence Scheme with Improved Intertask Locality," Proc. of Supercomputing '94, pages 773-782, 1994. |
| 60. |
D.K.Chen, J.Torrellas and P.C.Yew, "An Efficient Algorithm for the Run-Time Parallelization of Doacross Loops," Proc. of Supercomputing '94, pages 518-527, 1994. |
| 61. |
D.K.Poulsen and P.C. Yew, "Execution-Driven Tools for Parallel Simulation of Parallel Architecture and Applications," Proc. of Supercomputing '93, pages 860-869, November 1993. |
| 62. |
D.J. Kuck, et. al, "The Cedar System and an Initial Performance Study," Proc. of the 20th ACM/IEEE Symp. on Computer Architecture (ISCA-20), pages pp.213-223, May 1993. |
| 63. |
D.K. Chen and P.C. Yew, "Efficient Synchronization for Doacross Loops Execution," Proc. of 1992 Int'l Conf. on Parallel Processing (ICPP), August 1992. |
| 64. |
W.T. Hsu and P.C. Yew, "The Impact of Wiring Constraints on Hierarchical Network Performance," Proc. of the 1992 Int'l Parallel Processing Symp. (IPPS), pages 580-588, March 1992. |
| 65. |
P. Konas and P.C. Yew, "Synchronous Parallel Discrete Event Simulation on Shared-Memory Multiprocessors," Proc. of the 6th Workshop on Parallel and Distributed Simulation, pages 12-21, January 1992. |
| 66. |
H.M. Su and P.C. Yew, "Efficient Doacross Execution for Distributed Shared-Memory Systems," Proc. of Supercomputing '91, pages 842-853, November 1991. |
| 67. |
D.K. Chen and P.C. Yew, "An Empirical Study on Doacross Loops," Proc. of Supercomputing '91, pages 620-632, November 1991. |
| 68. |
W.T. Hsu and P.C. Yew, "The Performance of Hierarchical Systems with Wiring Constraints," Proc. of the 1991 Int'l Conf. on Parallel Processing (ICPP), volume 1, pages 9-16, August 1991. |
| 69. |
J.Konicek, et al, "The Organization of the Cedar System," Proc. of 1991 Int'l Conf. on Parallel Processing (ICPP), pages pp.49-56, August 1991. |
| 70. |
H.M. Su and P.C. Yew, "Efficient Interprocessor Communication on Distributed Shared-Memory Multiprocessors," Proc. of the 1991 Int'l Conf. on Parallel Processing (ICPP), volume 1, pages 45-48, August 1991. |
| 71. |
D.J. Lilja and P.C. Yew, "Combining Hardware and Software Cache Coherence Strategies," Proc. of the 1991 Int't Conf. on Supercomputing, pages 274-283, June 1991. |
| 72. |
H.B. Lim and P.C. Yew, "Parallel Program Behavioral Study on a Shared-Memory Multiprocessor," Proc. of the 1991 Int'l Conf. on Supercomputing (ICS), pages 386-395, June 1991. |
| 73. |
W. T. Hsu and P.C. Yew, "An Effective Synchronization Network for Large Multiprocessor Systems," Proc. of the 5th Int'l Parallel Processing Symp (IPPS), pages 309-317, May 1991. |
| 74. |
P. Konas, P.C. Yew, "Parallel Event Discrete Event Driven Simulation on Shared-Memory Multiprocessors," Proc. of the 24th Annual Simulation Symp., pages 134-148, April 1991. |
| 75. |
J. Bruner, H. Cheong, A. Veidenbaum and P. C. Yew, "Chief: A Parallel Simulation Environment for Parallel Systems," Proc. of the 5th Int'l Parallel Processing Symp (IPPS), pages 568-575, April 1991. |
| 76. |
P.C. Yew and J. Bruner, "SEE: A System Evaluation Environment for Studying Parallel Systems," Proc. of the First Workshop on Parallel Processing, December 1990. |
| 77. |
D. Lilja and P.C. Yew, "Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors and Multiprocessors," Proc. of 1990 Int'l Conf. on Parallel Processing (ICPP), pages 563-564, August 1990. |
| 78. |
D.K.Chen, H.M. Su and P.C. Yew, "The Impact of Synchronization and Granularity on Parallel Systems," Proc. of 17th ACM/IEEE International Symp. on Computer Architecture (ISCA-17), pages 239-249, June 1990. |
| 79. |
P. Tang, P.C. Yew and C.Q. Zhu, "Compiler Algorithms for Data Synchronization in Nested Parallel Loops," Proc. of 1990 Int'l Conf. on Supercomputing (ICS), pages 177-186, June 1990. |
| 80. |
P.Y. Tang and P.C. Yew, "A Parallel Linked List for Shared-Memory Multiprocessors," Proc. of the 1989 Computer Software and Application Conf., pages 130-135, October 1989. |
| 81. |
Z. Shen, Z. Li and P.C. Yew, "An Empirical Study on Array Subscripts and Data Dependences," Proc. of the 1989 Int'l Conf. on Parallel Processing (ICPP), pages 145-152, August 1989. |
| 82. |
Z. Li, P.C. Yew and C.Q. Zhu, "Data Dependence Analysis on Multi-Dimensional Array References," International Conf on Supercomputing, pages 215-224, June 1989. |
| 83. |
P.A. Emrath, D.A. Padua and P.C. Yew, "Cedar Architecture and Its Software," 22nd Hawaii Intn'l Conf. on System Sciences, pages 306-315, January 1989. |
| 84. |
H.M. Su and P.C. Yew, "On Data Synchronization for Multiprocessors," Proc. of the 16th ACM/IEEE International Symp. on Computer Architecture (ISCA-16), pages 416-423, 1989. |
| 85. |
Z. Li and P.C. Yew, "Efficient Interprocedural Analysis for Parallel Programs," ACM SIGPLAN Symp. on Parallel Programming: Experience with Applications, Languages and Systems, pages 85-99, July 1988. |
| 86. |
Z. Li and P.C. Yew, "Interprocedural Analysis for Parallel Computing," Proc. of the 1988 Int'l Conf. on Parallel Processing (ICPP), pages 221-228, 1988. |
| 87. |
P. Tang, P.C. Yew and C.Q. Zhu, "Impact of Self-Scheduling Order on Performance of Multiprocessor Systems," Proc. of the 1988 Int'l Conf. on Supercomputing (ICS), pages 593-603, 1988. |
| 88. |
Z. Fang, P.Y. Tang and P.C. Yew, C.Q. Zhu, "Dynamic Processor Self-Scheduling for General Parallel Nested Loops," Proc. of the 1987 Int'l Conf. on Parallel Processing (ICPP), pages 1-10, 1987. |
| 89. |
W.T. Hsu and P.C. Yew, "A Scheme to Enhance Binary N-Cube Networks," Proc. of the 1987 Int'l Conf. on Parallel Processing (ICPP), pages 820-823, 1987. |
| 90. |
R.L. Lee, P.C. Yew and D.H. Lawrie, "Data Prefetching in Shared Memory Multiprocessors," Proc. of the 1987 Int'l Conf. on Parallel Processing (ICPP), pages 28-31, 1987. |
| 91. |
R.L. Lee, P.C. Yew and D.H. Lawrie, "Multiprocessor Cache Design Considerations," Proc. of the 14th ACM/IEEE International Symp. on Computer Architecture (ISCA-14), pages 253-262, 1987. |
| 92. |
P.Y. Tang and P.C. Yew, "Deadlock Prevention in Processor Self-Scheduling for Nested Parallel Loops," Proc. of the 1987 Int'l Conf. on Parallel Processing (ICPP), pages 11-18, 1987. |
| 93. |
P.Y. Tang and P.C. Yew, "Processor Self-Scheduling for Multiple-Nested Parallel Loops," Proc. of the 1986 Int'l Conf. on Parallel Processing (ICPP), pages 528-535, August 1986, St. Charles, IL. |
| 94. |
N.F. Tzeng, P.C. Yew and C.Q. Zhu, "Fault-Diagnosis in a Multiple-Path Interconnection Networks," Proc. of the 16th Int'l Symp.on Fault-Tolerance Computing, pages 98-103, July 1986. |
| 95. |
N.F. Tzeng, P.C. Yew and C.Q. Zhu, "The Performance of A Fault-Tolerant Multistage Interconnection Network," Proc. of the 1985 Int'l Conf. on Parallel Processing (ICPP), pages 458-465, August 1985. |
| 96. |
N.F. Tzeng, P.C. Yew and C.Q. Zhu, "A Fault-Tolerant Scheme for Multistage Interconnection Networks," Proc. of the 12th ACM/IEEE Intl Symp. on Computer Architecture (ISCA-12), pages 368-375, June 1985. |
| 97. |
Q.X. Xu and P.C. Yew, "Simulations and Analysis for a Multiprocessor System with Multiprogramming," Proc. of the First Int'l Conf. on Computers and Applications, June 1984. |
| 98. |
C.Q. Zhu and P.C. Yew, "A Synchronization Scheme and Its Applications for Large Multiprocessor Systems," Proc. of the 4th Int'l Conf. on Distributed Computing Systems, pages 486-493, May 1984. |
| 99. |
P.Y. Chen, P.C. Yew and D.H. Lawrie, "Performance of Packet Switching in a Buffered Single-Stage Shuffle-Exchange Network," Proc. of the 3rd Int'l Conf. on Distributed Computing Systems, pages 622-629, October 1982. |
| 100. |
W. Abu-Sufah, R. Lee, M. Malkawi and P.C. Yew, "Experimental Results on the Paging Behavior of Numerical Programs," Proc. of the 6th Int'l Conf. on Software Engineering, pages 110-117, September 1982. |
| 101. |
J.E. Lilienkamp, D.H. Lawrie and P.C. Yew, "A Fault Tolerant Interconnection Networks Using Error Correcting Codes," Proc. of the 1982 Int'l Conf. on Parallel Processing (ICPP), pages 123-125, August 1982. |
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| Book & Book Chapters | | |
| 1. |
D.Kaeli and P.C. Yew, "Speculative Execution in High Performance Computer Architectures," CRC Press, 2005. |
| 2. |
G.H. Lee and P.C. Yew, "The Kluwer International Series in Engineering and Computer Science," Kluwer Academic Publishers, 2002. |
| 3. |
S. Chatterjee, et al, "Lecture Notes in Computer Science," Springer, 1998. |
| 4. |
Z. Li, P.C. Yew, et al, "Languages and Compilers for Parallel Computing," Lecture Notes in Computer Science, 1997. |
| 5. |
Z. Li and P.C. Yew,, chapter "Some Results on Exact Data Dependence Analysis," Languages and Compilers for Parallel Computing, D. Gerlenter, editor, pages 374-401, A. Nicolau and D. Padua (Pitman/MIT Press), 1990. |
| 6. |
P.C. Yew,, chapter "Architecture of the Cedar Parallel Supercomputer, IParallel Systems and Computation," North-Holland, Amesterdam, G. Almasi and R. Hockney and G. Paul, editors, pages 137-148, North-Holland, Amesterdam, 1988. |
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