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Digital Logic Design Lab (訾頛航身閮撖衣), Fall 2010


Announcement
Lecturing Information
Slides
Grading
Lecturing Information (隤脩鞈閮)
Class Information

Lecturer

Reference Books

Syllabus
  1. 隤脩隞蝝孵頛臬祕撽函陛隞
  2. 訾 IC 隤霅頛舐皜祈岫隤踵
  3. 箸祇頛舫銋隤霅皜祈岫
  4. 銝璆菟銋雿輻
  5. TTL CMOS ａ餉楝
  6. Quartus II 雿輻函陛隞 VHDL 蝪∩
  7. AND, OR, NOT 蝯餉楝撖阡
  8. NAND, NOR 蝯餉楝撖阡
  9. 鈭脖皜瘜券餉楝閮剛
  10. 蝺函Ⅳ/閫蝣澆券餉楝撖阡憭撌/閫憭撌亙券餉楝撖阡
  11. 蝪⊥撖蝣潮餉楝閮剛
  12. 貊Ⅳ頧餉楝閮剛BCD 瘜券＊蝷粹餉楝閮剛
  13. 甇其摨
  14. 甇亙甇亥詨
  15. 蝘颱怠具摨餉楝銋閮剛
  16. 閮嗥隞嗉身閮

Grading
  • 隤脣撖阡雿撖阡勗嚗 40%
    銝剛嚗 30%
    怨嚗 30%

Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson
Digital Design, 4th Edition, by M. Morris Mano and Michael D. Ciletti, Pearson
     


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Yuan-Hao Chang
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