Digital Logic Design Lab (數位邏輯設計實習), Spring 2011

Digital Logic Design Lab (�訾��讛摩閮剛�撖衣�), Spring 2011

	Announcement
	Lecturing Information
	Slides
	Grading

Lecturing Information (隤脩�鞈��)

Class Announcement

Go to Announcement

Class Information

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Lecturing hours: 3:10 pm ~ 6:00 pm, Thursday
Classroom: 蝬𦦵� 501 (�餉楝撖阡�: 蝬𦦵� 105)
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Lecturing hours: 3:10 pm ~ 6:00 pm, Friday
Classroom: 蝬𦦵� 502 (�餉楝撖阡�: 蝬𦦵� 105)
Class webpage: http://www.ntut.edu.tw/~johnsonchang/courses/DLDL201102/

Lecturer

Yuan-Hao Chang (撘萄�鞊�)
Office: Room 207-2
Tel: +886-2-2771-2171 ext. 2288
Email: johnsonchang[at]ntut.edu.tw
Home page: http://www.ntut.edu.tw/~johnsonchang/

Reference Books

Syllabus

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�訾� IC ��霅䁅��讛摩��讠�皜祈岫隤踵㟲
�箸𧋦�讛摩�䀝�隤滩��葫閰�
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TTL �� CMOS �屸𢒰�餉楝
Quartus II 雿輻鍂蝪∩�� VHDL 蝪∩�
AND, OR, NOT 蝯��餉楝撖阡�
NAND, NOR 蝯��餉楝撖阡�
鈭屸�脖��䭾�瘜訫膥�餉楝閮剛�
蝺函Ⅳ/閫�Ⅳ�券𤓖頝臬祕撽𨰜��撌�/閫��撌亙膥�餉楝撖阡�
蝪⊥�撖�Ⅳ�㚚𤓖頝航身閮�
�貊Ⅳ頧㗇��餉楝閮剛��BCD �䭾��券＊蝷粹𤓖頝航身閮�
甇��其��
�𧼮�甇亙��峕郊閮�彍��
蝘颱��怠��具��煾𤓖頝臭��身閮�
閮䀹�蝯�辣閮剛�

Grading

隤脣�撖阡��滢��𠰴祕撽堒𥼚�𠺪� 80%
�煺葉�� 10%
��錰�� 10%

Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson

Digital Design, 4th Edition, by M. Morris Mano and Michael D. Ciletti, Pearson

Yuan-Hao Chang
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